The invention relates to a method for fabricating a semiconductor device. More specifically, the invention relates to a method for fabricating a storage electrode of a semiconductor device.
The reduction of the design rule for semiconductor memory devices has brought about technical difficulties in fabricating memory devices within a limited area. For example, it is difficult to fabricate dynamic random access memory (DRAM) devices comprising a plurality of memory cell units each including a transistor and a capacitor while ensuring a sufficient capacitance within a limited area.
To ensure continuous data storage in volatile memory (e.g., DRAM) devices, electrical charges must be periodically introduced into cells, a process referred to as a “refresh” process. The refresh process requires high power consumption, thus disadvantageously affecting mobile products. In an attempt to solve this problem, prolongation of the period between refresh processes has been suggested. The prolongation of the refresh period requires an increase in capacitance (Cs) of the storage capacitor in each cell unit, or a decrease in the parasitic capacitance (Cb) of the cell unit.
To ensure sufficient capacitance of the storage capacitor, various methods directed to increasing the effective surface area of a storage electrode have been considered. First of all, an increased storage electrode height is being preferentially considered. In particular, to obtain an increased effective surface area, trends toward increasingly taller cylinder-type storage electrodes continue.
To obtain an increased effective surface area, there has been suggested a method for forming an uneven electrode pattern via the difference in etching ratio after depositing plasma enhanced tetraorthosilicate (PE-TEOS) on phospho-silicate glass (PSG). However, since the difference in etching ratio between PE-TEOS and PSG is considerably large, a very complicated etching process in the formation of a storage electrode is required. A simplification in the etching process may cause formation of a bridge on the interface between the PE-TEOS and PSG, or permeation of the titanium (Ti) and titanium nitride (TiN) into the interface during subsequent processes. Trends toward lightweight, thin, short and small devices reduce the gap between adjacent storage electrodes, thus making it considerably difficult to solve these problems.
In addition, since PSG is relatively flowable, a reduced storage electrode width results in geometric instability of an electrode pattern, thus causing the “leaning” phenomenon. Accordingly, there has been an increased demand for a method to increase the effective surface area of storage electrodes having a limited height.